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cy8c24x93 psoc ? programmable system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-86894 rev. *b revised may 24, 2013 psoc ? programmable system-on-chip features powerful harvard-architecture processor ? m8c cpu with a max speed of 24 mhz operating range: 1.71 v to 5.5 v ? standby mode 1.1 a (typ) ? deep sleep 0.1 a (typ) operating temperature range: ?40 c to +85 c flexible on-chip memory ? 8 kb flash, 1 kb sram ? 16 kb flash, 2 kb sram ? 32 kb flash, 2 kb sram ? read while write with eeprom emulation ? 50,000 flash erase/write cycles ? in-system programming simplif ies manufacturing process four clock sources ? internal main oscillato r (imo): 6/12/24 mhz ? internal low-speed oscillator (ilo) at 32 khz for watchdog and sleep timers ? external 32 khz crystal oscillator ? external clock input programmable pin configurations ? up to 36 general purpose dual mode gpio (analog inputs and digital i/o supported) ? high sink current of 25 ma per gpio ? max sink current 120 ma for all gpios ? source current ? 5 ma on ports 0 and 1 ? 1 ma on ports 2,3 and 4 ? configurable internal pull-up, high-z and open drain modes ? selectable, regulated digital i/o on port 1 ? configurable input threshold on port 1 versatile analog functions ? internal low-dropout voltage regulator for high power supply rejection ratio (psrr) full-speed usb ? 12 mbps usb 2.0 compliant ? eight unidirectional endpoints ? one bidirectional endpoint ? dedicated 512 byte sram ? no external crystal required additional system resources ? i2c slave: ? selectable to 50 khz, 100 khz, or 400 khz ? configurable up to 12 mhz spi master and slave ? three 16-bit timers ? watchdog and sleep timers ? integrated supervisory circuit ? 10-bit incremental analog-to-digital converter (adc) with internal voltage reference ? two general-purpose comparators ? 3 voltage references (0.8 v, 1 v, 1.2 v) ? any pin to either comparator inputs ? low-power operation at 10 a ? one 8-bit idac with full scale range of 512 a ? one 8-bit software pwm development platform ? psoc designer? ide gpios and package options ? 13 gpios - qfn 16 ? 28 gpios - qfn 32 ? 34 gpios - qfn 48 ? 36 gpios - qfn 48
cy8c24x93 document number: 001-86894 rev. *b page 2 of 65 logic block diagram analog system 1k/2k sram interrupt controller sleep and watchdog multiple clock sources internal low speed oscillator (ilo) 6/12/24 mhz internal main oscillator (imo) psoc core cpu core (m8c) supervisory rom (srom) 8k/16k/32k flash nonvolatile memory system resources system bus analog reference system bus port 3 port 2 port 1 port 0 adc global analog interconnect 1.8/2.5/3v ldo analog mux i2c slave spi master/ slave por and lvd usb system resets internal voltage references three 16-bit programmable timers pwrsys (regulator) port 4 digital clocks idac two comparators [1] note 1. internal voltage regulator for internal circuitry.
cy8c24x93 document number: 001-86894 rev. *b page 3 of 65 contents psoc ? functional overview ............................................ 5 psoc core .................................................................. 5 analog system ....... .............. .............. .............. ............ 5 additional system resources ..................................... 6 getting started .................................................................. 7 silicon errata ............................................................... 7 development kits ........................................................ 7 training ....................................................................... 7 cypros consultants .................................................... 7 solutions library .......................................................... 7 technical support ....................................................... 7 development tools .......................................................... 8 psoc designer software subsyst ems .......... .............. 8 designing with psoc designer ....................................... 9 select user modules ................................................... 9 configure user modules .............................................. 9 organize and connect .............. .............. ........... ......... 9 generate, verify, and debug ....................................... 9 pinouts ............................................................................ 10 16-pin qfn (13 gpios) [2] .. ...................................... 10 32-pin qfn (28 gpios) [6] .. ...................................... 11 32-pin qfn (28 gpios) [10] ...................................... 12 48-pin qfn (34 gpios) [14] ...................................... 13 48-pin qfn (36 gpios (with usb)) [19] ................... 14 48-pin qfn (ocd) (36 gpios) [23] .......................... 15 electrical specifications (cy8 c24193/493) .................. 16 absolute maximum ratings (cy8c24193/493) ............................................................. 16 operating temperature (cy8c24193/493) ............................................................. 16 dc chip-level specifications (cy8c24193/493) ............................................................. 17 dc gpio specifications (cy8c24193/493) ............................................................. 18 dc analog mux bus specifications (cy8c24193/493) ............................................................. 21 dc low power comparator specifications (cy8c24193/493) ............................................................. 21 comparator user module el ectrical specifications (cy8c24193/493) ............................................................. 21 adc electrical specifications (cy8c24193/493) ............................................................. 22 dc por and lvd specifications (cy8c24193/493) ............................................................. 23 dc programming specifications (cy8c24193/493) ............................................................. 23 dc i2c specifications (cy8c24193/493) ............................................................. 24 shield driver dc specifications (cy8c24193/493) ............................................................. 24 dc idac specifications (cy8c24193/493) ............................................................. 24 ac chip-level specifications (cy8c24193/493) ............................................................. 25 ac general purpose i/o specifications (cy8c24193/493) ............................................................. 26 ac comparator specifications (cy8c24193/493) ............................................................. 26 ac external clock specifications (cy8c24193/493) ............................................................. 26 ac programming specifications (cy8c24193/493) ............................................................. 27 ac i2c specifications (cy8 c24193/493) . ............ ..... 28 electrical specifications (cy8c24093/293/393/693) ............................................... 31 absolute maximum ratings (cy8c24093/293/393/693) ............................................... 31 operating temperature (cy8c24093/293/393/693) ............................................... 31 dc chip-level specifications (cy8c24093/293/393/693) ............................................... 32 dc gpio specifications (cy8c24093/293/393/693) ............................................... 33 dc analog mux bus specifications (cy8c24093/293/393/693) ............................................... 35 dc low power comparator specifications (cy8c24093/293/393/693) ............................................... 35 comparator user module el ectrical specifications (cy8c24093/293/393/693) ............................................... 36 adc electrical specifications (cy8c24093/293/393/693) ............................................... 36 dc por and lvd specifications (cy8c24093/293/393/693) ............................................... 37 dc programming specifications (cy8c24093/293/393/693) ............................................... 37 dc i2c specifications (cy8c24093/293/393/693) ............................................... 38 dc reference buffer specifications (cy8c24093/293/393/693) ............................................... 38 dc idac specifications (cy8c24093/293/393/693) ............................................... 38 ac chip-level specifications (cy8c24093/293/393/693) ............................................... 39 ac gpio specifications (cy8c24093/293/393/693) ............................................... 40 ac comparator specifications (cy8c24093/293/393/693) ............................................... 41 ac external clock specifications (cy8c24093/293/393/693) ............................................... 41 ac programming specifications (cy8c24093/293/393/693) ............................................... 42 ac i2c specifications (cy8c24093/293/393/693) ............................................... 43 packaging information ................................................... 46 thermal impedances ................................................. 49 capacitance on crystal pins .. ............. .............. ........ 49 solder reflow specifications ..................................... 49 development tool selection .. .............. .............. ........... 50 software .................................................................... 50
cy8c24x93 document number: 001-86894 rev. *b page 4 of 65 development kits ...................................................... 50 evaluation tools ........................................................ 50 device programmers ................................................. 50 ordering information ...................................................... 51 ordering code definitions ......................................... 51 acronyms ........................................................................ 52 document conventions ................................................. 53 units of measure ....................................................... 53 reference documents .................................................... 53 numeric naming ............................................................. 53 glossary .......................................................................... 54 appendix a: silicon errata for the cy8c24093/293/393/693 family ..................................... 55 cy8c24093/293/393/693 qualific ation status .......... 55 cy8c24093/293/393/693 errata summary ............... 55 appendix b: silico n errata for the psoc? cy8c24193/493 families ............... ........... ........ 60 cy8c24193/493 qualification st atus .......... .............. 60 cy8c24193/493 errata summary .......... ........... ........ 60 document history page ................................................. 64 sales, solutions, and legal information ...................... 65 worldwide sales and design s upport ......... .............. 65 products .................................................................... 65 psoc solutions ......................................................... 65
cy8c24x93 document number: 001-86894 rev. *b page 5 of 65 psoc ? functional overview the psoc family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (mcu)-based components with one, low cost single-chip programmable component. a psoc device includes configurable analog and digital blocks, and programmable interconnect. this architecture allows the user to create customized peripheral configurat ions, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the architecture for this device family, as shown in the logic block diagram on page 2 , consists of three main areas: the core analog system system resources (including a full-speed usb port). a common, versatile bus allows connection between i/o and the analog system. depending on the psoc package, up to 36 gpio are included in the cy8c24x93 psoc device. the gpio provides access to the mcu and analog mux. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo and ilo. the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a 4-mips, 8-bit harvard-architecture microprocessor. analog system the analog system is composed of an adc, two comparators and an idac. it has an internal 0.8 v, 1 v or 1.2 v analog reference. all the pins can be c onfigured to connect to the analog system. adc the adc in the cy8c24x93 device is an incremental analog-to-digital converter with a range of 8 to 10 bits supporting signed and unsigned data formats. the input to the adc can be from any pin. idac the idac can provide current source up to 512 a to any gpio pin. in the cy8c24x93 family of devices 4 ranges of current source can be implemented that can vary in 255 steps, and are connected to analog mux bus. comparator the cy8c24x93 family has two high-speed, low-power comparators. the comparators have three voltage references, 0.8 v, 1.0 v and 1.2 v. comparat or inputs can be connected from any pin through the analog mux bus. the comparator output can be read in firmware for processing or routed out via specific pins (p1_0 or p1_4). the output of the two comparator s can be combined with 2-input logic functions. the combinatorial output can be optionally combined with a latched value and routed to a pin output or to the interrupt controller. the input multiplexers and the comparator are controller th rough the cmp user module. table 1. idac ranges range full scale range in a 1x 64 2x 128 4x 256 8x 512
cy8c24x93 document number: 001-86894 rev. *b page 6 of 65 analog multiplexer system the analog mux bus can connect to every gpio pin and can be internally connected to the adc, comprators or the idac. other multiplexer applications include: chip-wide mux that allows analog input from any i/o pin. crosspoint connection between any i/o pin combinations. additional system resources system resources provide additional capability, such as configurable usb and i2c slave, spi master/slave communication interface, three 16-bit programmable timers, software 8-bit pwm, low voltage detect, power on reset, and various system resets supported by the m8c. the merits of each system resource are listed here: the i 2 c slave/spi master-slave module provides 50/100/400 khz communication over two wires. spi communication over three or f our wires runs at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). low-voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced power-on-reset (por) circuit e liminates the need for a system supervisor. a register-controlled bypass mode allows the user to disable the ldo regulator. an 8-bit software pwm is provided for applications like buzzer control or lighting control. a 16-bi t timer acts as the input clock to the pwm. the isr increments a software counter (8-bit), checks for pwm compare condition and toggles a gpio accordingly. pwm output is available on all gpios.
cy8c24x93 document number: 001-86894 rev. *b page 7 of 65 getting started the quickest way to understand psoc silicon is to read this datasheet and then use the psoc designer integrated development environment (ide). this datasheet is an overview of the psoc integrated circuit and pr esents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the technical reference manual for the psoc devices. for up-to-date ordering, packaging , and electrical specification information, see the latest psoc device datasheets on the web at www.cypress.com/psoc . silicon errata errata documents known issues with silicon including errata trigger conditions, scope of impact, available workarounds and silicon revision applicability. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics a nd skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736.
cy8c24x93 document number: 001-86894 rev. *b page 8 of 65 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requirements. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical us er interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/transmitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (dacs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this lets you to use more than 100 percent of psoc?s resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs fo r the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu regist ers, set and clear breakpoints, and provide program run, halt , and step control. the debugger also lets you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. th is system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation.
cy8c24x93 document number: 001-86894 rev. *b page 9 of 65 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of use r-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules?. user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pwm user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width an d duty cycle. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development en vironment lets you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full-speed. psoc designer debugging capabilities rival those of syst ems costing many times more. in addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.
cy8c24x93 document number: 001-86894 rev. *b page 10 of 65 pinouts 16-pin qfn (13 gpios) [2] table 2. pin definitions ? cy8c24093 [3] pin no. type name description figure 1. cy8c24093 device digital analog 1 i/o i p2[5] crystal output (xout) 2 i/o i p2[3] crystal input (xin) 3 iohr i p1[7] i 2 c scl, spi ss 4 iohr i p1[5] i 2 c sda, spi miso 5 iohr i p1[3] spi clk 6 iohr i p1[1] issp clk [4] , i 2 c scl, spi mosi 7 power v ss ground connection 8 iohr i p1[0] issp data [4] , i 2 c sda, spi clk [5] 9 iohr i p1[2] 10 iohr i p1[4] optional external clock (extclk) 11 input xres active high external reset with internal pull-down 12 ioh i p0[4] 13 power v dd supply voltage 14 ioh i p0[7] 15 ioh i p0[3] 16 ioh i p0[1] legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. qfn (top view) ai , xout, p2[5] ai , i2 c scl, spi ss, p1[7] ai , i2 c sda, spi miso, p1[5] ai, spi cl k , p1[3] 1 2 3 4 11 10 9 16 15 14 13 p0[3], ai p0[7], ai v dd p0[4] , ai ai, issp clk, spi mosi, p1[1] ai, issp data , i2c sda, spi cl k , p1[0] p1[2] , ai ai , xin, p2[3] p1[4] , extclk, ai xres p0[1], ai v ss 12 5 6 7 8 notes 2. no center pad. 3. 13 gpios. 4. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep c lock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i 2 c bus. use alternate pins if you encounter issues. 5. alternate spi clock.
cy8c24x93 document number: 001-86894 rev. *b page 11 of 65 32-pin qfn (28 gpios) [6] table 3. pin definitions ? cy8c24193 [7] pin no. type name description figure 2. cy8c24193 digital analog 1 ioh i p0[1] 2 i/o ip2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o ip3[3] 7 i/o i p3[1] 8 iohr i p1[7] i 2 c scl, spi ss 9 iohr i p1[5] i 2 c sda, spi miso 10 iohr i p1[3] spi clk. 11 iohr i p1[1] issp clk [8] , i 2 c scl, spi mosi. 12 power v ss ground connection. 13 iohr i p1[0] issp data [8] , i 2 c sda, spi clk [9] 14 iohr i p1[2] 15 iohr i p1[4] optional external clock input (extclk) 16 iohr i p1[6] 17 input xres active high external reset with internal pull-down 18 i/o ip3[0] 19 i/o ip3[2] 20 i/o ip2[0] 21 i/o i p2[2] 22 i/o i p2[4] 23 i/o i p2[6] 24 ioh i p0[0] 25 ioh i p0[2] 26 ioh i p0[4] 27 ioh i p0[6] 28 power v dd supply voltage 29 ioh i p0[7] 30 ioh i p0[5] 31 ioh i p0[3] 32 power v ss ground connection cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai , p0[1] ai , p2[7] ai , xout, p2[5] ai , xin, p2[3] ai , p2[1] ai , p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0 [3 ], ai p0 [7 ], ai vd d p0 [6 ], ai p0 [4 ], ai p0 [2 ], ai ai , p3[1] ai , i2 c scl, spi ss, p1[7] p0[0] , ai p2[6] , ai p3[0] , ai xres ai, i 2c sda, sp i miso, p 1[5] ai, spi clk, p1[3] vss ai, p 1[ 2] ai, e xtclk , p 1[ 4] ai, p 1[ 6] p2[4] , ai p2[2] , ai p2[0] , ai p3[2] , ai p0 [5 ], ai ai , issp clk , i2c scl, spi mosi, p1[1] ai , issp d ata , i2c sda, spi clk, p1[0] [8] [8] notes 6. 28 gpios. 7. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 8. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep c lock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 9. alternate spi clock.
cy8c24x93 document number: 001-86894 rev. *b page 12 of 65 32-pin qfn (28 gpios) [10] table 4. pin definitions ? cy8c24293 [11] pin no. digital analog name description figure 3. cy8c24293 device 1 ioh i p0[1] 2 i/o i p2[5] crystal output (xout) 3 i/o i p2[3] crystal input (xin) 4 i/o i p2[1] 5 i/o i p4[3] 6 i/o i p3[3] 7 i/o i p3[1] 8 iohr i p1[7] i 2 c scl, spi ss 9 iohr i p1[5] i 2 c sda, spi miso 10 iohr i p1[3] spi clk. 11 iohr i p1[1] issp clk [12] , i 2 c scl, spi mosi. 12 power v ss ground connection 13 iohr i p1[0] issp data [12] , i 2 c sda, spi clk [13] 14 iohr i p1[2] 15 iohr i p1[4] optional external clock input (extclk) 16 iohr i p1[6] 17 input xres active high external reset with internal pull-down 18 i/o i p3[0] 19 i/o i p3[2] 20 i/o i p4[0] 21 i/o i p4[2] 22 i/o i p2[0] 23 i/o i p2[2] 24 i/o i p2[4] 25 ioh i p0[0] 26 ioh i p0[2] 27 ioh i p0[4] 28 ioh i p0[6] 29 power v dd 30 ioh i p0[7] 31 ioh i p0[3] 32 power v ss ground connection cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai , p0[1] ai , p2[5] ai , xout , p2[3] ai , xin , p2[1] ai , p4[3] ai , p3[3] qfn (top view ) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vs s p0 [3 ], ai p0[6], ai v dd p0 [4 ], ai p0 [2 ], ai p0 [0 ], ai ai , p3[1] ai , i2 c scl, spi ss, p1[7] p2[4] , ai p2[2] , ai p3[0] , ai xres ai, i2c sda , spi mi so, p 1[ 5] ai, spi clk, p1[3] vss ai , p 1[ 2] ai, extclk, p 1[ 4] ai , p 1[ 6] p2[0] , ai p4[2] , ai p4[0] , ai p3[2] , ai p0 [7 ], ai ai , issp clk , i2c scl, spi mosi, p1[1] ai ,issp d at a , i 2 c s da , s pi c l k, p 1[ 0] [12] [12] notes 10. 28 gpios. 11. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 12. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 13. alternate spi clock.
cy8c24x93 document number: 001-86894 rev. *b page 13 of 65 48-pin qfn (34 gpios) [14] table 5. pin definition s ? cy8c24393, cy8c24693 [15, 16] pin no. digital analog name description figure 4. cy8c24393, cy8c24693 device 1 nc no connection 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o i p4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] issp clk [17] , i 2 c scl, spi mosi 18 power v ss ground connection 19 nc no connection 20 nc no connection 21 power v dd supply voltage pin no. digital analog name description 22 iohr i p1[0] issp data [17] , i 2 c sda, spi clk [18] 36 nc no connection 23 iohr i p1[2] 37 ioh i p0[0] 24 iohr i p1[4] optional external clock input (extclk) 38 ioh i p0[2] 25 iohr i p1[6] 39 ioh i p0[4] 26 input xres active high external reset with internal pull-down 40 ioh i p0[6] 27 i/o i p3[0] 41 power v dd supply voltage 28 i/o i p3[2] 42 nc no connection 29 i/o i p3[4] 43 nc no connection 30 i/o i p3[6] 44 ioh i p0[7] 31 i/o i p4[0] 45 nc no connection 32 i/o i p4[2] 46 ioh i p0[3] 33 i/o i p2[0] 47 power v ss ground connection 34 i/o i p2[2] 48 ioh i p0[1] 35 i/o i p2[4] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view) vss p0[3], ai nc , p0[7], ai vd d p0[6], ai p0[2], ai p0[0], ai 10 11 12 ai , p2[7] nc ai, xout, p2[5] ai , xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai p3[1] ai, i2 c scl, spi ss, p1 [7 ] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 4 6 45 44 43 42 41 4 0 39 38 37 p2[4], ai p2[2], ai p2[0], ai p4[2], ai p4[0], ai p3[6], ai p3[4], ai p3[2], ai p3[0], ai xres p1[6], ai nc 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi mis o, a i, p1[5] nc spiclk,ai, p1[3] ai, issp c lk, i2c scl, spi mosi, p1[1] vss nc nc vdd ai, issp data 1 , i2c sda, spi clk, p1[0] ai, p1[2] ai, extclk, p1[4] nc nc nc p0[4], ai p0[1], ai notes 14. 38 gpios. 15. this part is available in limited quantities for in-circuit debugging during prototype developm ent. it is not available in p roduction volumes. 16. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 17. on power-up, the sda(p1[0]) drives a strong high for 256 sle ep clock cycles and drives resi stive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transiti on to high impedance state. on reset, after xres de- asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high imped ance state. in both cases, a pull-up resistance on these lin es combines with the pull-down resistance (5.6k ohm) and form a potential divider. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use al ternate pins if you encounter issues. 18. alternate spi clock.
cy8c24x93 document number: 001-86894 rev. *b page 14 of 65 48-pin qfn (36 gpios (with usb)) [19] table 6. pin definitions ? cy8c24493 [20, 21] pin no. digital analog name description figure 5. cy8c24493 1 nc no connection 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o i p4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] issp clk [20] , i 2 c scl, spi mosi 18 power v ss ground connection 19 i/o d+ usb d+ 20 i/o d- usb d- 21 power v dd supply voltage 22 iohr i p1[0] issp data [20] , i 2 c sda, spi clk [22] 23 iohr i p1[2] 24 iohr i p1[4] optional external clock input (extclk) 25 iohr i p1[6] 26 input xres active high external reset with internal pull-down 27 i/o i p3[0] 28 i/o i p3[2] 29 i/o i p3[4] pin no. digital analog name description 30 i/o i p3[6] 40 ioh i p0[6] 31 i/o i p4[0] 41 power v dd supply voltage 32 i/o i p4[2] 42 nc no connection 33 i/o i p2[0] 43 nc no connection 34 i/o i p2[2] 44 ioh i p0[7] 35 i/o i p2[4] 45 ioh i p0[5] 36 i/o i p2[6] 46 ioh i p0[3] 37 ioh i p0[0] 47 power v ss ground connection 38 ioh i p0[2] 48 ioh i p0[1] 39 ioh i p0[4] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai ai , p2[7] nc ai , xout, p2[5] ai , xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai , p3[1] ai , i2 c scl, spi ss, p1[7] 35 34 33 32 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4] , ai p2[2] , ai p2[0] , ai p4[2] , ai p2[6] , ai 1 2 3 4 5 nc nc p0[4], ai p0[1], ai (top view) 10 11 12 31 30 29 28 27 26 25 p4[0] , ai p3[6] , ai p3[4] , ai p3[2] , ai p3[0 ], ai xres p1[6] , ai 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, a i, p1[5] nc spi clk, a i, p1[3] ai , issp cl k ,i2cscl,spimosi,p1[1] vss d+ d- vdd ai , issp data, i2c sda, spi cl k ,p1[0] ai, p 1[ 2 ] ai, extclk, p1[4] nc [20, 22] [20] notes 19. 36 gpios. 20. on power-up, the sda(p1[0]) drives a strong high for 256 sle ep clock cycles and drives resi stive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on re set, after xres de- asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high imped ance state. in both cases, a pull-up resistance on these lin es combines with the pull-down resistance (5.6k ohm) and form a potential divider. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use al ternate pins if you encounter issues. 21. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 22. alternate spi clock.
cy8c24x93 document number: 001-86894 rev. *b page 15 of 65 48-pin qfn (ocd) (36 gpios) [23] the 48-pin qfn part is for the cy8c240093 on-chip debug (ocd). note that this part is only used for in-circuit debugging. table 7. pin definitions ? cy8c240093 [24, 25] pin no. digital analog name description figure 6. cy8c240093 1 [26] ocdoe ocd mode direction pin 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o i p4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 [26] cclk ocd cpu clock output 15 [26] hclk ocd high speed clock output 16 iohr i p1[3] spi clk. 17 iohr i p1[1] issp clk [ 27 ], i 2 c scl, spi mosi 18 power v ss ground connection 19 i/o d+ usb d+ 20 i/o d- usb d- 21 power v dd supply voltage 22 iohr i p1[0] issp data [ 27 ] , i 2 c sda, spi clk [ 28 ] 23 iohr i p1[2] pin no. digital analog name description 24 iohr i p1[4] optional external clock input (extclk) 37 ioh i p0[0] 25 iohr i p1[6] 38 ioh i p0[2] 26 input xres active high external reset with internal pull-down 39 ioh i p0[4] 27 i/o i p3[0] 40 ioh i p0[6] 28 i/o i p3[2] 41 power v dd supply voltage 29 i/o i p3[4] 42 [26] ocdo ocd even data i/o 30 i/o i p3[6] 43 [26] ocde ocd odd data output 31 i/o i p4[0] 44 ioh i p0[7] 32 i/o i p4[2] 45 ioh i p0[5] 33 i/o i p2[0] 46 ioh i p0[3] 34 i/o i p2[2] 47 power v ss ground connection 35 i/o i p2[4] 48 ioh i p0[1] 36 i/o i p2[6] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view) vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 a i , p2[7] ai , xout, p2[5] ai , xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai , p3[1] ai , i2 c scl, spi ss, p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4] , ai p2[2] , ai p2[0] , ai p4[2] , ai p4[0] , ai p3[6] , ai p3[4] , ai p3[2] , ai p3[0] , ai xres p1[6] , ai p2[6] , ai 1 2 3 4 5 6 7 8 9 1 3 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, ai, p1[5] spi clk, a i, p1[3] ai , issp clk 6 , i2c scl, spi mosi, p1[1] vss d+ d- vdd ai,issp data 1 , i2c sda, spi clk, p1[0] ai, p 1 [ 2 ] ai, extclk, p1[4] p0[4], ai p0[1], ai ocdo e cclk hclk ocde ocdo [27, 28] [27] notes 23. 36 gpios. 24. this part is available in limited quantities for in-circuit debugging during prototype developm ent. it is not available in p roduction volumes. 25. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 26. this pin (associated with ocd part only) is required for connec ting the device to ice-cube in-circuit emulator for firmware debugging purpose. to know more about the usage of ice-cube, refer to cy3215-dk psoc ? in-circuit emulator kit guide . 27. on power-up, the sda(p1[0]) drives a strong high for 256 sle ep clock cycles and drives resi stive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transiti on to high impedance state. on reset, after xres de- asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high imped ance state. in both cases, a pull-up resistance on these lin es combines with the pull-down resistance (5.6k ohm) and form a potential divider. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use al ternate pins if you encounter issues. 28. alternate spi clock.
cy8c24x93 document number: 001-86894 rev. *b page 16 of 65 electrical specificatio ns (cy8c24193/493) this section presents the dc and ac elec trical specifications of the cy8c24193/493 psoc devices. for the latest electrical specifications, confirm that you have the mo st recent datasheet by visiting the web at http://www.cypress.com/psoc . figure 7. voltage versus cpu frequency absolute maximum ratings (cy8c24193/493) exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature (cy8c24193/493) 5.5 v 750 khz 24 mhz cpu frequency v dd voltage 1. 71 v 3 mhz v a l i d o p e r a t i n g r e g i o n table 8. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 c degrades reliability. ?55 +25 +125 c v dd supply voltage relative to v ss ? ?0.5 ? +6.0 v v io dc input voltage ? v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tristate ? v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ? ?25 ? +50 ma esd electro static discharge voltage human body model esd 2000 ? ? v lu latch up current in accordance with jesd78 standard ? ? 200 ma table 9. operating temperature symbol description conditions min typ max units t a ambient temperature ? ?40 ? +85 c t c commercial temperature range ? 0 70 c t j operational die temperature the temperature rise from ambient to junction is package specific. see the thermal impedances on page 49 . the user must limit the power consumption to comply with this requirement. ?40 ? +100 c
cy8c24x93 document number: 001-86894 rev. *b page 17 of 65 dc chip-level specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 10. dc chip-level specifications symbol description conditions min typ max units v dd [29, 43] supply voltage see table dc por and lvd specifications (cy8c24093/293/393/693) on page 37 1.71 ? 5.50 v i dd24 supply current, imo = 24 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 24 mhz. ? 2.88 4.00 ma i dd12 supply current, imo = 12 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 12 mhz. ? 1.71 2.60 ma i dd6 supply current, imo = 6 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 6 mhz. ? 1.16 1.80 ma i sb0 deep sleep current v dd ? 3.0 v, t a = 25 c, i/o regulator turned off ? 0.10 1.1 ? a i sb1 standby current with por, lvd and sleep timer v dd ? 3.0 v, t a = 25 c, i/o regulator turned off ? 1.07 1.50 ? a i sbi2c standby current with i 2 c enabled conditions are v dd = 3.3 v, t a = 25 c and cpu = 24 mhz ? 1.64 ? ? a notes 29. when v dd remains in the range from 1.71 v to 1.9 v for more than 50 s, the slew rate when moving from the 1.71 v to 1.9 v range to gre ater than 2 v must be slower than 1 v/500 s to avoid triggering por. the only other restriction on slew rates for any other voltage range or transit ion is the sr power_up parameter. 30. if powering down in standby sleep mode , to properly detect and recover from a v dd brown out condition any of the following actions must be taken: a. bring the device out of sleep before powering down. b. assure that v dd falls below 100 mv before powering back up. c. set the no buzz bit in the osc_cr0 register to k eep the voltage monitoring circuit powered during sleep. d. increase the buzz rate to assure that the falling edge of v dd is captured. the rate is configured through the pssdc bits in the slp_cfg register. for the referenced registers, refer to the technical reference manual . in deep sleep/standby sleep mode, additional low power voltage monitoring circuitry allows v dd brown out conditions to be detected and resets the device when v dd goes lower than 1.1 v at edge rates slower than 1 v/ms.
cy8c24x93 document number: 001-86894 rev. *b page 18 of 65 dc gpio specifications (cy8c24193/493) the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 11. 3.0 v to 5.5 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 pins i oh = 1 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 5 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh < 10 ? a, v dd > 3.1 v, maximum of 4 i/os all sourcing 5 ma 2.85 3.00 3.30 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh = 5 ma, v dd > 3.1 v, maximum of 20 ma source current in all i/os 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh < 10 ? a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh = 2 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.60 1.80 2.10 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage i ol = 25 ma, v dd > 3.3 v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? ? 0.80 v v ih input high voltage ? 2.00 ? ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 0.00 1 1 ? a c pin pin capacitance package and pin dependent te m p = 2 5 c 0.50 1.70 7 pf v illvt3.3 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.8 v ? ? v ihlvt3.3 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.4 ? ? v v illvt5.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.8 v ? ? v ihlvt5.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.7 ? ? v
cy8c24x93 document number: 001-86894 rev. *b page 19 of 65 table 12. 2.4 v to 3.0 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd - 0.20 ? ? v v oh2 high output voltage port 2 or 3 pins i oh = 0.2 ma, maximum of 10 ma source current in all i/os v dd - 0.40 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd - 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v dd - 0.50 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.50 1.80 2.10 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage i ol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? ? 0.72 v v ih input high voltage ? 1.40 ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent te m p = 2 5 ? c 0.50 1.70 7 pf v illvt2.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.7 v ? v ihlvt2.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.2 ? v
cy8c24x93 document number: 001-86894 rev. *b page 20 of 65 table 13. 1.71 v to 2.4 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 pins i oh = 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 pins i oh = 0.5 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 100 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v ol low output voltage i ol = 5 ma, maximum of 20 ma sink current on even port pi ns (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.40 v v il input low voltage ? ? ? 0.30 v dd v v ih input high voltage ? 0.65 v dd ??v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 ? c 0.50 1.70 7 pf table 14. gpio current sink and source specifications supply voltage mode port 1 per i/o (max) port 2/3/4 per i/o (max) total current even pins (max) total current odd pins (max) units 1.71 ? 2.4 sink 5 5 20 30 ma source 2 0.5 10 [31] ma 2.4 ? 3.0 sink 10 10 30 30 ma source 2 0.2 10 [31] ma 3.0 ? 5.0 sink 25 25 60 60 ma source 5 1 20 [31] ma note 31. total current (odd + even ports)
cy8c24x93 document number: 001-86894 rev. *b page 21 of 65 dc analog mux bus specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc low power comparator spec ifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. comparator user module electrica l specifications (cy8c24193/493) the following table lists the guaranteed maximum and minimum spec ifications. unless stated otherwis e, the specifications are fo r the entire device voltage and temperature operating range: ?40 c ? ta ? 85 c, 1.71 v ? v dd ? 5.5 v. table 15. dc analog mux bus specifications symbol description conditions min typ max units r sw switch resistance to common analog bus ? ? ? 800 ? r gnd resistance of initialization switch to v ss ? ? ? 800 ? the maximum pin voltage for measuring r sw and r gnd is 1.8 v table 16. dc comparator specifications symbol description conditions min typ max units v lpc low power comparator (lpc) common mode maximum voltage limited to v dd 0.2 ? 1.8 v i lpc lpc supply current ? ? 10 80 ? a v oslpc lpc voltage offset ? ? 2.5 30 mv table 17. comparator user module electrical specifications symbol description conditions min typ max units t comp comparator response time 50 mv overdrive ? 70 100 ns offset valid from 0.2 v to 1.5 v ? 2.5 30 mv current average dc current, 50 mv overdrive ? 20 80 a psrr supply voltage > 2 v power supply rejection ratio ? 80 ? db supply voltage < 2 v power supply rejection ratio ? 40 ? db input range ? 0.2 1.5 v
cy8c24x93 document number: 001-86894 rev. *b page 22 of 65 adc electrical specific ations (cy8c24193/493) table 18. adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range ? 0 ? vrefadc v c iin input capacitance ???5 pf r in input resistance equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500ff data clock) 1/(400ff data clock) 1/(300ff data clock) ? reference v refadc adc reference voltage ? 1.14 ? 1.26 v conversion rate f clk data clock source is chip?s internal main oscillator. see ac chip-level specifications on page 25 for accuracy 2.25 ? 6 mhz s8 8-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ?23.43 ?ksps s10 10-bit sample rate da ta clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 5.85 ? ksps dc accuracy res resolution can be set to 8, 9, or 10 bit 8 ? 10 bits dnl differential nonlinearity ? ?1 ? +2 lsb inl integral nonlinearity ? ?2 ? +2 lsb e offset offset error 8-bit resolution 0 3.20 19.20 lsb 10-bit resolution 0 12.80 76.80 lsb e gain gain error for any resolution ?5 ? +5 %fsr power i adc operating current ? ? 2.10 2.60 ma psrr power supply rejection ratio psrr (v dd > 3.0 v) ? 24 ? db psrr (v dd < 3.0 v) ? 30 ? db
cy8c24x93 document number: 001-86894 rev. *b page 23 of 65 dc por and lvd specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc programming specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 19. dc por and lvd specifications symbol description conditions min typ max units v por0 1.66 v selected in psoc designer v dd must be greater than or equal to 1.71 v during startup, reset from the xres pin, or reset from watchdog. 1.61 1.66 1.71 v v por1 2.36 v selected in psoc designer ? 2.36 2.41 v por2 2.60 v selected in psoc designer ? 2.60 2.66 v por3 2.82 v selected in psoc designer ? 2.82 2.95 v lvd0 2.45 v selected in psoc designer ? 2.40 2.45 2.51 v v lvd1 2.71 v selected in psoc designer 2.64 [46] 2.71 2.78 v lvd2 2.92 v selected in psoc designer 2.85 [47] 2.92 2.99 v lvd3 3.02 v selected in psoc designer 2.95 [48] 3.02 3.09 v lvd4 3.13 v selected in psoc designer 3.06 3.13 3.20 v lvd5 1.90 v selected in psoc designer 1.84 1.90 2.32 v lvd6 1.80 v selected in psoc designer 1.75 [49] 1.80 1.84 v lvd7 4.73 v selected in psoc designer 4.62 4.73 4.83 table 20. dc programming specifications symbol description conditions min typ max units v ddiwrite supply voltage for flash write operations ? 1.71 ? 5.25 v i ddp supply current during programming or verify ? ? 5 25 ma v ilp input low voltage during programming or verify see appropriate dc gpio specifications (cy8c24093/293/393/693) on page 33 ? ? v il v v ihp input high voltage during programming or verify see appropriate dc gpio specifications (cy8c24093/293/393/693) on page 33 v ih ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 0.2 ma i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 1.5 ma v olp output low voltage during programming or verify ? ? v ss + 0.75 v v ohp output high voltage during programming or verify see appropriate dc gpio specifications (cy8c24093/293/393/693) on page 33 . for v dd > 3v use v oh4 in table 36 on page 33 . v oh ? v dd v flash enpb flash write endurance erase/write cycles per block 50,000 ? ? ? flash dr flash data retention following maximum flash write cycles; ambient temperature of 55 c 20 ? ? years notes 32. always greater than 50 mv above v ppor1 voltage for falling supply. 33. always greater than 50 mv above v ppor2 voltage for falling supply. 34. always greater than 50 mv above v ppor3 voltage for falling supply. 35. always greater than 50 mv above v ppor0 voltage for falling supply.
cy8c24x93 document number: 001-86894 rev. *b page 24 of 65 dc i 2 c specifications (cy8c24193/493) the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. shield driver dc specifications (cy8c24193/493) the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc idac specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 21. dc i 2 c specifications [36] symbol description conditions min typ max units v ili2c input low level 3.1 v v dd 5.5 v ? ? 0.25 v dd v 2.5 v v dd 3.0 v ? ? 0.3 v dd v 1.71 v v dd 2.4 v ? ? 0.3 v dd v v ihi2c input high level 1.71 v v dd 5.5 v 0.65 v dd ?v dd + 0.7 v [37] v table 22. shield driver dc specifications symbol description conditions min typ max units v ref reference buffer output 1.7 v v dd 5.5 v 0.942 ? 1.106 v v refhi reference buffer output 1.7 v v dd 5.5 v 1.104 ? 1.296 v table 23. dc idac specifications (8-bit idac) symbol description min typ max units notes idac_dnl differential nonlinearity ?1 ? 1 lsb idac_dnl integral nonlinearity ?2 ? 2 lsb idac_current range = 4x 138 ? 169 a dac setting = 127 dec range = 8x 138 ? 169 a dac setting = 64 dec table 24. dc idac specifications (7-bit idac) symbol description min typ max units notes idac_dnl differential nonlinearity ?1 ? 1 lsb idac_dnl integral nonlinearity ?2 ? 2 lsb idac_current range = 4x 137 ? 168 a dac setting = 127 dec range = 8x 138 ? 169 a dac setting = 64 dec notes 36. pull-up resistors on i2c int erface cannot be connected to a supp ly voltage that is more than 0.7 v higher than the cy8c24x93 power supply. see the cy8c24x93 silicon errata document for more details. 37. please refer to item # 6 of the cy8c24x93 family.
cy8c24x93 document number: 001-86894 rev. *b page 25 of 65 ac chip-level specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 25. ac chip-level specifications symbol description conditions min typ max units f imo24 imo frequency at 24 mhz setting ? 22.8 24 25.2 mhz f imo12 imo frequency at 12 mhz setting ? 11.4 12 12.6 mhz f imo6 imo frequency at 6 mhz setting ? 5.7 6.0 6.3 mhz f cpu cpu frequency ? 0.75 ? 25.20 mhz f 32k1 ilo frequency ? 15 32 50 khz f 32k_u ilo untrimmed frequency ? 13 32 82 khz dc imo duty cycle of imo ? 40 50 60 % dc ilo ilo duty cycle ? 40 50 60 % sr power_up power supply slew rate v dd slew rate during power-up ? ? 250 v/ms t xrst external reset pulse width at power-up after supply voltage is valid 1 ? ? ms t xrst2 external reset pulse width after power-up [50] applies after part has booted 10 ? ? ? s t jit_imo [39] 6 mhz imo cycle-to-cycle jitter (rms) ? ? 0.7 6.7 ns 6 mhz imo long term n cycle-to-cycle jitter (rms); n = 32 ? ? 4.3 29.3 ns 6 mhz imo period jitter (rms) ? ? 0.7 3.3 ns 12 mhz imo cycle-to-cycle jitter (rms) ? ? 0.5 5.2 ns 12 mhz imo long term n cycle-to-cycle jitter (rms); n = 32 ? ? 2.3 5.6 ns 12 mhz imo period jitter (rms) ? ? 0.4 2.6 ns 24 mhz imo cycle-to-cycle jitter (rms) ? ? 1.0 8.7 ns 24 mhz imo long term n cycle-to-cycle jitter (rms); n = 32 ? ? 1.4 6.0 ns 24 mhz imo period jitter (rms) ? ? 0.6 4.0 ns note 38. the minimum required xres pulse length is longer when programming the device (see table 55 on page 42 ). 39. see the cypress jitter sp ecifications application note, understanding datasheet jitter specific ations for cypress timing products ? an5054 for more information.
cy8c24x93 document number: 001-86894 rev. *b page 26 of 65 ac general purpose i/o specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 8. gpio timing diagram ac comparator specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac external clock specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 26. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode port 0, 1 0 0 ? ? 6 mhz for 1.71 v cy8c24x93 document number: 001-86894 rev. *b page 27 of 65 ac programming specifications (cy8c24193/493) figure 9. ac waveform the following table lists the guaranteed maximum and minimum s pecifications for the entire vo ltage and temperature ranges. table 29. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk ? 1 ? 20 ns t fsclk fall time of sclk ? 1 ? 20 ns t ssclk data setup time to falling edge of sclk ? 40 ? ? ns t hsclk data hold time from falling edge of sclk ? 40 ? ? ns f sclk frequency of sclk ? 0 ? 8 mhz t eraseb flash erase time (block) ? ? ? 18 ms t write flash block write time ? ? ? 25 ms t dsclk data out delay from falling edge of sclk 3.6 ? v dd ? ? 60 ns t dsclk3 data out delay from falling edge of sclk 3.0 ? v dd ? 3.6 ? ? 85 ns t dsclk2 data out delay from falling edge of sclk 1.71 ? v dd ? 3.0 ? ? 130 ns t xrst3 external reset pulse width after power-up required to enter programming mode when coming out of sleep 300 ? ? ? s t xres xres pulse length ? 300 ? ? ? s t vddwait v dd stable to wait-and-poll hold off ? 0.1 ? 1 ms t vddxres v dd stable to xres assertion delay ? 14.27 ? ? ms t poll sdat high pulse time ? 0.01 ? 200 ms t acq ?key window? time after a v dd ramp acquire event, bas ed on 256 ilo clocks. ? 3.20 ? 19.60 ms t xresini ?key window? time after an xres event, based on 8 ilo clocks ? 98 ? 615 ? s sclk (p1[1]) t rsclk t fsclk sdata (p1[0]) t ssclk t hsclk t dsclk
cy8c24x93 document number: 001-86894 rev. *b page 28 of 65 ac i 2 c specifications (cy8c24193/493) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 10. definition for timing for fast/standard mode on the i 2 c bus table 30. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time (repeated) start condition. afte r this period, the first clock pulse is generated 4.0 ?0.6 ?s t low low period of the scl clock 4.7 ?1.3 ?s t high high period of the scl clock 4.0 ?0.6 ?s t su;sta setup time for a repeated start condition 4.7 ?0.6 ?s t hd;dat [40] data hold time 20 3.45 20 0.90 s t su;dat data setup time 250 ? 100 [53] ?ns t su;sto setup time for stop condition 4.0 ?0.6 ?s t buf bus free time between a stop and start condition 4.7 ?1.3 ?s t sp pulse width of spikes are suppressed by the input filter ? ?050ns notes 40. to wake up from sleep using i2c hardware addr ess match event, i2c interface needs 20 ns hold time on sda line with respect to falling edge of scl. see the cy8c24x93 silicon errata document for more details. 41. a fast-mode i 2 c-bus device can be used in a standard mode i 2 c-bus system, but the requirement t su;dat ? 250 ns must then be met. this automatically be the case if the device does not stre tch the low period of the scl signal. if such devi ce does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released.
cy8c24x93 document number: 001-86894 rev. *b page 29 of 65 figure 11. spi master mode 0 and 2 figure 12. spi master mode 1 and 3 table 31. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd ? ? 2.4 v v dd < 2.4 v ? ? ? ? 6 3 mhz mhz dc sclk duty cycle ? ? 50 ? % t setup miso to sclk setup time v dd ? 2.4 v v dd < 2.4 v 60 100 ? ? ? ? ns ns t hold sclk to miso hold time ? 40 ? ? ns t out_val sclk to mosi valid time ? ? ? 40 ns t out_h mosi high time ? 40 ? ? ns 1/f sclk t low t high t out_h t hold t setup t out_su msb lsb spi master, modes 0 and 2 sclk (mode 0) sclk (mode 2) miso (input) mosi (output) 1/f sclk t high t low t out_h t hold t setup sclk (mode 1) sclk (mode 3) miso (input) mosi (output) spi master, modes 1 and 3 t out_su msb msb lsb lsb
cy8c24x93 document number: 001-86894 rev. *b page 30 of 65 figure 13. spi slave mode 0 and 2 figure 14. spi slave mode 1 and 3 table 32. spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency ? ? ? 4 mhz t low sclk low time ? 42 ? ? ns t high sclk high time ? 42 ? ? ns t setup mosi to sclk setup time ? 30 ? ? ns t hold sclk to mosi hold time ? 50 ? ? ns t ss_miso ss high to miso valid ? ? ? 153 ns t sclk_miso sclk to miso valid ? ? ? 125 ns t ss_high ss high time ? 50 ? ? ns t ss_clk time from ss low to first sclk ? 2/sclk ? ? ns t clk_ss time from last sclk to ss high ? 2/sclk ? ? ns t clk_ss t ss_high 1/f sclk t low t high t out_h t hold t setup t ss_miso t ss_clk msb lsb spi slave, modes 0 and 2 /ss sclk (mode 0) sclk (mode 2) miso (output) mosi (input) t clk_ss 1/f sclk t high t low t sclk_miso t out_h t hold t setup t ss_clk /ss sclk (mode 1) sclk (mode 3) miso (output) mosi (input) spi slave, modes 1 and 3 t ss_miso msb msb lsb lsb
cy8c24x93 document number: 001-86894 rev. *b page 31 of 65 electrical specifications (cy8c24093/293/393/693) this section presents the dc and ac electric al specifications of the cy8c24093/293/393/693 psoc devices. for the latest electri cal specifications, confirm that you have the mo st recent datasheet by visiting the web at http://www.cypress.com/psoc . figure 15. voltage versus cpu frequency absolute maximum ratings (cy8c24093/293/393/693) exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature (cy8c24093/293/393/693) 5.5v 750 khz 24 mhz cpu frequency vdd voltage 1.71v 3 mhz v a l i d o p e r a t i n g r e g i o n table 33. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 c degrades reliability. ?55 +25 +125 c v dd supply voltage relative to v ss ? ?0.5 ? +6.0 v v io dc input voltage ? v ss ? 0.5 ? v dd + 0.5 v v ioz [42] dc voltage applied to tristate ? v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ? ?25 ? +50 ma esd electrostatic discharge voltage human body model esd 2000 ? ? v lu latch-up current in accordance with jesd78 standard ? ? 200 ma table 34. operating temperature symbol description conditions min typ max units t a ambient temperature ? ?40 ? +85 c t c commercial temperature range ? 0 70 c t j operational die temperature the temperature rise from ambient to junction is package specific. refer the thermal impedances on page 49 . the user must limit the power consumption to comply with this requirement. ?40 ? +100 c note 42. port1 pins are hot-swap capable with i/o configur ed in high-z mode, and pin input voltage above v dd .
cy8c24x93 document number: 001-86894 rev. *b page 32 of 65 dc chip-level specificati ons (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 35. dc chip-level specifications symbol description conditions min typ max units v dd [43, 44, 45] supply voltage no usb activity. refer the table dc por and lvd specifications (cy8c24093/293/393/693) on page 37 1.71 ? 5.50 v v ddusb [43, 44, 45] operating voltage usb activity, usb regulator enabled 4.35 ? 5.25 v usb activity, usb regulator bypassed 3.15 3.3 3.60 v i dd24 supply current, imo = 24 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 24 mhz. no i/o sourcing current ? ? 4.00 ma i dd12 supply current, imo = 12 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 12 mhz. no i/o sourcing current ? ? 2.60 ma i dd6 supply current, imo = 6 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 6 mhz. no i/o sourcing current ? ? 1.80 ma i sb0 deep sleep current v dd ? 3.0 v, t a = 25 c, i/o regulator turned off ? 0.10 1.05 ? a i sb1 standby current with por, lvd and sleep timer v dd ? 3.0 v, t a = 25 c, i/o regulator turned off ? 1.07 1.50 ? a i sbi2c standby current with i 2 c enabled conditions are v dd = 3.3 v, t a = 25 c and cpu = 24 mhz ? 1.64 ? ? a notes 43. when v dd remains in the range from 1.71 v to 1.9 v for more than 50 s, t he slew rate when moving from the 1.71 v to 1.9 v range to gre ater than 2 v must be slower than 1 v/500 s to avoid triggering por. the only other re striction on slew rates for any other voltage range or transit ion is the sr power_up parameter. 44. if powering down in standby sleep mode, to properly detect and recover from a v dd brown out condition any of the following actions must be taken: a.bring the device out of sleep before powering down. b.assure that v dd falls below 100 mv before powering back up. c.set the no buzz bit in the osc_cr0 register to k eep the voltage monitoring circuit powered during sleep. d.increase the buzz rate to assu re that the falling edge of v dd is captured. the rate is configured th rough the pssdc bits in the slp_cfg register. for the referenced registers, refer to the cy8c24x93 technical reference manual . in deep sleep mode, additional low power voltage monitoring circuitry allows v dd brown out conditions to be detected for edge rates slower than 1v/ms. 45. for usb mode, the v dd supply for bus-powered application should be limited to 4.35 v?5.35 v. for self-powered application, v dd should be 3.15 v?3.45 v.
cy8c24x93 document number: 001-86894 rev. *b page 33 of 65 dc gpio specifications (cy8c24093/293/393/693) the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 36. 3.0 v to 5.5 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 1 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 5 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh < 10 ? a, v dd > 3.1 v, maximum of 4 i/os all sourcing 5 ma 2.85 3.00 3.30 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh = 5 ma, v dd > 3.1 v, maximum of 20 ma source current in all i/os 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh < 10 ? a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh = 2 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.60 1.80 2.10 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage i ol = 25 ma, v dd > 3.3 v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.75v v il input low voltage ? ? ? 0.80 v v ih input high voltage ? 2.00 ? ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 0.001 1 ? a c pin pin capacitance package and pin dependent te m p = 2 5 c 0.50 1.70 7 pf v illvt3.3 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.8 v ? ? v ihlvt3.3 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.4 ? ? v v illvt5.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.8 v ? ? v ihlvt5.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.7 ? ? v
cy8c24x93 document number: 001-86894 rev. *b page 34 of 65 table 37. 2.4 v to 3.0 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 0.2 ma, maximum of 10 ma source current in all i/os v dd ? 0.40 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.50 1.80 2.10 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? ? 0.72 v v ih input high voltage ? 1.40 ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 ? c 0.50 1.70 7 pf v illvt2.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.7 v ? v ihlvt2.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.2 ? v table 38. 1.71 v to 2.4 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh = 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 0.5 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 100 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v ol low output voltage i ol = 5 ma, maximum of 20 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.40 v
cy8c24x93 document number: 001-86894 rev. *b page 35 of 65 dc analog mux bus specifications (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc low power comparator specifications (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. v il input low voltage ? ? ? 0.30 v dd v v ih input high voltage ? 0.65 v dd ??v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 c 0.50 1.70 7 pf table 38. 1.71 v to 2.4 v dc gpio specifications (continued) symbol description conditions min typ max units table 39. dc characteristics ? usb interface symbol description conditions min typ max units r usbi usb d+ pull-up resistance with idle bus 900 ? 1575 ? r usba usb d+ pull-up resistance while receiving traffic 1425 ? 3090 ? v ohusb static output high ? 2.8 ?3.6v v olusb static output low ? ? ?0.3v v di differential input sensitivity ? 0.2 ?v v cm differential input common mode range ? 0.8 ?2.5v v se single ended receiver threshold ? 0.8 ?2.0v c in transceiver capacitance ? ? ?50pf i io high z state data line leakage on d+ or d- line ?10 ?+10 ? a r ps2 ps/2 pull-up resistance ? 3000 5000 7000 ? r ext external usb series resistor in se ries with each usb pin 21.78 22.0 22.22 ? table 40. dc analog mux bus specifications symbol description conditions min typ max units r sw switch resistance to common analog bus ? ? ? 800 ? r gnd resistance of initialization switch to v ss ? ? ? 800 ? the maximum pin voltage for measuring r sw and r gnd is 1.8 v table 41. dc comparator specifications symbol description conditions min typ max units v lpc low power comparator (lpc) common mode maximum voltage limited to v dd 0.0 ? 1.8 v i lpc lpc supply current ? ? 10 40 ? a v oslpc lpc voltage offset ? ? 3 30 mv
cy8c24x93 document number: 001-86894 rev. *b page 36 of 65 comparator user module electrical sp ecifications (cy8c24093/293/393/693) the following table lists the guaranteed maximum and minimum spec ifications. unless stated otherwis e, the specifications are fo r the entire device voltage and temperature operating range: ?40 c ? t a ? 85 c, 1.71 v ? v dd ? 5.5 v. adc electrical specifications (cy8c24093/293/393/693) table 42. comparator user module electrical specifications symbol description conditions min typ max units t comp comparator response time 50 mv overdrive ? 70 100 ns offset valid from 0.2 v to v dd ? 0.2 v ? 2.5 30 mv current average dc current, 50 mv overdrive ? 20 80 a psrr supply voltage > 2 v power supply rejection ratio ? 80 ? db supply voltage < 2 v power supply rejection ratio ? 40 ? db input range ? 0 1.5 v table 43. adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range ? 0 ? vrefadc v c iin input capacitance ???5pf r in input resistance equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500ff data clock) 1/(400ff data clock) 1/(300ff data clock) ? reference v refadc adc reference voltage ? 1.14 ? 1.26 v conversion rate f clk data clock source is chip?s internal main oscillator. see ac chip-level specifications for accuracy 2.25 ? 6 mhz s8 8-bit sample rate data cl ock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 23.43 ? ksps s10 10-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 5.85 ? ksps dc accuracy res resolution can be set to 8-, 9-, or 10-bit 8 ? 10 bits dnl differential nonlinearity ? ?1 ? +2 lsb inl integral nonlinearity ? ?2 ? +2 lsb e offset offset error 8-bit resolution 0 3.20 19.20 lsb 10-bit resolution 0 12.80 76.80 lsb e gain gain error for any re solution ?5 ? +5 %fsr power i adc operating current ? ? 2.10 2.60 ma psrr power supply rejection ratio psrr (v dd > 3.0 v) ? 24 ? db psrr (v dd < 3.0 v) ? 30 ? db
cy8c24x93 document number: 001-86894 rev. *b page 37 of 65 dc por and lvd specificati ons (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc programming specifications (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 44. dc por and lvd specifications symbol description conditions min typ max units v por0 1.66 v selected in psoc designer v dd must be greater than or equal to 1.71 v during startup, reset from the xres pin, or reset from watchdog. 1.61 1.66 1.71 v v por1 2.36 v selected in psoc designer ? 2.36 2.41 v por2 2.60 v selected in psoc designer ? 2.60 2.66 v por3 2.82 v selected in psoc designer ? 2.82 2.95 v lvd0 2.45 v selected in psoc designer ? 2.40 2.45 2.51 v v lvd1 2.71 v selected in psoc designer 2.64 [46] 2.71 2.78 v lvd2 2.92 v selected in psoc designer 2.85 [47] 2.92 2.99 v lvd3 3.02 v selected in psoc designer 2.95 [48] 3.02 3.09 v lvd4 3.13 v selected in psoc designer 3.06 3.13 3.20 v lvd5 1.90 v selected in psoc designer 1.84 1.90 2.32 v lvd6 1.80 v selected in psoc designer 1.75 [49] 1.80 1.84 v lvd7 4.73 v selected in psoc designer 4.62 4.73 4.83 table 45. dc programming specifications symbol description conditions min typ max units v ddiwrite supply voltage for flash write operations ? 1.71 ? 5.25 v i ddp supply current during programming or verify ? ? 5 25 ma v ilp input low voltage during programming or verify see the appropriate dc gpio specifications (cy8c24093/293/393/693) on page 33 ? ? v il v v ihp input high voltage during programming or verify see the appropriate dc gpio specifications (cy8c24093/293/393/693) on page 33 v ih ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 0.2 ma i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 1.5 ma v olp output low voltage during programming or verify ? ? v ss + 0.75 v v ohp output high voltage during programming or verify see appropriate dc gpio specifications (cy8c24093/293/393/693) on page 33 . for v dd > 3 v use v oh4 in table 34 on page 31. v oh ? v dd v flash enpb flash write endurance erase/write cycles per block 50,000 ? ? ? flash dr flash data retention following maximum flash write cycles; ambient temperature of 55 c 20 ? ? years notes 46. always greater than 50 mv above v ppor1 voltage for falling supply. 47. always greater than 50 mv above v ppor2 voltage for falling supply. 48. always greater than 50 mv above v ppor3 voltage for falling supply. 49. always greater than 50 mv above v ppor0 voltage for falling supply.
cy8c24x93 document number: 001-86894 rev. *b page 38 of 65 dc i 2 c specifications (cy8c24093/293/393/693) the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc reference buffer specifications (cy8c24093/293/393/693) the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc idac specifications (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 46. dc i 2 c specifications symbol description conditions min typ max units v ili2c input low level 3.1 v v dd 5.5 v ? ? 0.25 v dd v 2.5 v v dd 3.0 v ? ? 0.3 v dd v 1.71 v v dd 2.4 v ? ? 0.3 v dd v v ihi2c input high level 1.71 v v dd 5.5 v 0.65 v dd ??v table 47. dc reference buffer specifications symbol description conditions min typ max units v ref reference buffer output 1.7 v v dd 5.5 v 1 ? 1.05 v v refhi reference buffer output 1.7 v v dd 5.5 v 1.2 ? 1.25 v table 48. dc idac specifications symbol description min typ max units notes idac_dnl differential nonlinearity ?4.5 ? +4.5 lsb idac_inl integral nonlinearity ?5 ? +5 lsb idac_gain (source) range = 0.5x 6.64 ? 22.46 a dac setting = 128 dec range = 1x 14.5 ? 47.8 a range = 2x 42.7 ? 92.3 a range = 4x 91.1 ? 170 a dac setting = 128 dec range = 8x 184.5 ? 426.9 a dac setting = 128 dec
cy8c24x93 document number: 001-86894 rev. *b page 39 of 65 ac chip-level specificati ons (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 49. ac chip-level specifications symbol description conditions min typ max units f imo24 imo frequency at 24 mhz setting ? 22.8 24 25.2 mhz f imo12 imo frequency at 12 mhz setting ? 11.4 12 12.6 mhz f imo6 imo frequency at 6 mhz setting ? 5.7 6.0 6.3 mhz f cpu cpu frequency ? 0.75 ? 25.20 mhz f 32k1 ilo frequency ? 15 32 50 khz f 32k_u ilo untrimmed frequency ? 13 32 82 khz dc imo duty cycle of imo ? 40 50 60 % dc ilo ilo duty cycle ? 40 50 60 % sr power_up power supply slew rate v dd slew rate during power-up ? ? 250 v/ms t xrst external reset pulse width at power-up after supply voltage is valid 1 ? ? ms t xrst2 external reset pulse width after power-up [50] applies after part has booted 10 ? ? ? s t os startup time of eco ??1?s t jit_imo [51] n=32 6 mhz imo cycle-to-cycle jitter (rms) ? 0.7 6.7 ns 6 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ? 4.3 29.3 ns 6 mhz imo period jitter (rms) ? 0.7 3.3 ns 12 mhz imo cycle-to-cycle jitter (rms) ? 0.5 5.2 ns 12 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ?2.35.6ns 12 mhz imo period jitter (rms) ? 0.4 2.6 ns 24 mhz imo cycle-to-cycle jitter (rms) ? 1.0 8.7 ns 24 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ?1.46.0ns 24 mhz imo period jitter (rms) ? 0.6 4.0 ns notes 50. the minimum required xres pulse length is longer when programming the device (see table 55 on page 42 ). 51. refer to cypress jitter specifications application note, understanding datasheet jitt er specifications for cypr ess timing products ? an5054 for more information.
cy8c24x93 document number: 001-86894 rev. *b page 40 of 65 ac gpio specifications (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 16. gpio timing diagram table 50. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode port 0, 1 0 0 ? ? 6 mhz for 1.71 v cy8c24x93 document number: 001-86894 rev. *b page 41 of 65 ac comparator specificati ons (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac external clock specifications (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 51. ac characteristics ? usb data timings symbol description conditions min typ max units t drate full speed data rate average bit rate 12 ? 0.25% 12 12 + 0.25% mhz t jr1 receiver jitter tolerance to next transition ?18.5 ? 18.5 ns t jr2 receiver jitter tolerance to pair transition ?9.0 ? 9 ns t dj1 fs driver jitter to next transition ?3.5 ? 3.5 ns t dj2 fs driver jitter to pair transition ?4.0 ? 4.0 ns t fdeop source jitter for differential transition to se0 transition ?2.0 ? 5 ns t feopt source se0 interval of eop ? 160.0 ? 175 ns t feopr receiver se0 interval of eop ? 82.0 ? ? ns t fst width of se0 interval during differential transition ???14ns table 52. ac characteristics ? usb driver symbol description conditions min typ max units t fr transition rise time 50 pf 4 ? 20 ns t ff transition fall time 50 pf 4 ? 20 ns t frfm [52] rise/fall time matching ? 90 ? 111 % v crs output signal crosso ver voltage ? 1.30 ? 2.00 v table 53. ac low power comparator specifications symbol description conditions min typ max units t lpc comparator response time, 50 mv overdrive 50 mv overdrive does not include offset voltage. ??100ns table 54. ac external clock specifications symbol description conditions min typ max units f oscext frequency (external oscillator frequency) ?0.75 ? 25.20 mhz high period ? 20.60 ? 5300 ns low period ? 20.60 ? ?ns power-up imo to switch ? 150 ? ? ? s note 52. t frfm is not met under all conditions. there is a corner case at lo wer supply voltages, such as thos e under 3.3 v. this condition do es not affect usb communications. signal integrity tests show an e xcellent eye diagram at 3.15 v.
cy8c24x93 document number: 001-86894 rev. *b page 42 of 65 ac programming specifications (cy8c24093/293/393/693) figure 17. ac waveform the following table lists the guaranteed maximum and minimum s pecifications for the entire vo ltage and temperature ranges. table 55. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk ? 1 ? 20 ns t fsclk fall time of sclk ? 1 ? 20 ns t ssclk data setup time to fa lling edge of sclk ? 40 ? ? ns t hsclk data hold time from falling edge of sclk ? 40 ? ? ns f sclk frequency of sclk ? 0 ? 8 mhz t eraseb flash erase time (block) ? ? ? 18 ms t write flash block write time ? ? ? 25 ms t dsclk data out delay from falling edge of sclk 3.6 ? v dd ? ? 60 ns t dsclk3 data out delay from falling edge of sclk 3.0 ? v dd ? 3.6 ? ? 85 ns t dsclk2 data out delay from falling edge of sclk 1.71 ? v dd ? 3.0 ? ? 130 ns t xrst3 external reset pulse width after power-up required to enter programming mode when coming out of sleep 300 ? ? ? s t xres xres pulse length ? 300 ? ? ? s t vddwait v dd stable to wait-and-poll hold off ? 0.1 ? 1 ms t vddxres v dd stable to xres assertion delay ? 14.27 ? ? ms t poll sdata high pulse time ? 0.01 ? 200 ms t acq ?key window? time after a v dd ramp acquire event, based on 256 ilo clocks. ? 3.20 ? 19.60 ms t xresini ?key window? time after an xres event, based on 8 ilo clocks ? 98 ? 615 ? s sclk (p1[1]) t rsclk t fsclk sdata (p1[0]) t ssclk t hsclk t dsclk
cy8c24x93 document number: 001-86894 rev. *b page 43 of 65 ac i 2 c specifications (cy8c24093/293/393/693) the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 18. definition for timing for fast/standard mode on the i 2 c bus table 56. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ?0.6 ?s t low low period of the scl clock 4.7 ?1.3 ?s t high high period of the scl clock 4.0 ?0.6 ?s t su;sta setup time for a repeated start condition 4.7 ?0.6 ?s t hd;dat data hold time 0 3.45 0 0.90 s t su;dat data setup time 250 ? 100 [53] ?ns t su;sto setup time for stop condition 4.0 ?0.6 ?s t buf bus free time between a stop and start condition 4.7 ?1.3 ?s t sp pulse width of spikes are suppressed by the input filter ? ?050ns note 53. a fast-mode i 2 c-bus device can be used in a standard mode i 2 c-bus system, but the requirement t su;dat ? 250 ns must then be met. this automatically be the case if the device does not stre tch the low period of the scl signal. if such devi ce does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) befor e the scl line is released.
cy8c24x93 document number: 001-86894 rev. *b page 44 of 65 figure 19. spi master mode 0 and 2 figure 20. spi master mode 1 and 3 table 57. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd ? ? 2.4 v v dd < 2.4 v ? ? ? ? 6 3 mhz mhz dc sclk duty cycle ? ? 50 ? % t setup miso to sclk setup time v dd ? 2.4 v v dd < 2.4 v 60 100 ? ? ? ? ns ns t hold sclk to miso hold time ? 40 ? ? ns t out_val sclk to mosi valid time ? ? ? 40 ns t out_h mosi high time ? 40 ? ? ns 1/f sclk t low t high t out_h t hold t setup t out_su msb lsb spi master, modes 0 and 2 sclk (mode 0) sclk (mode 2) miso (input) mosi (output) 1/f sclk t high t low t out_h t hold t setup sclk (mode 1) sclk (mode 3) miso (input) mosi (output) spi master, modes 1 and 3 t out_su msb msb lsb lsb
cy8c24x93 document number: 001-86894 rev. *b page 45 of 65 figure 21. spi slave mode 0 and 2 figure 22. spi slave mode 1 and 3 table 58. spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency ? ? ? 4 mhz t low sclk low time ? 42 ? ? ns t high sclk high time ? 42 ? ? ns t setup mosi to sclk setup time ? 30 ? ? ns t hold sclk to mosi hold time ? 50 ? ? ns t ss_miso ss high to miso valid ? ? ? 153 ns t sclk_miso sclk to miso valid ? ? ? 125 ns t ss_high ss high time ? 50 ? ? ns t ss_clk time from ss low to first sclk ? 2/sclk ? ? ns t clk_ss time from last sclk to ss high ? 2/sclk ? ? ns t clk_ss t ss_high 1/f sclk t low t high t out_h t hold t setup t ss_miso t ss_clk msb lsb spi slave, modes 0 and 2 /ss sclk (mode 0) sclk (mode 2) miso (output) mosi (input) t clk_ss 1/f sclk t high t low t sclk_miso t out_h t hold t setup t ss_clk /ss sclk (mode 1) sclk (mode 3) miso (output) mosi (input) spi slave, modes 1 and 3 t ss_miso msb msb lsb lsb
cy8c24x93 document number: 001-86894 rev. *b page 46 of 65 packaging information this section illustrates the packaging spec ifications for the cy8c24x93 psoc device, along with the thermal impedances for each package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . figure 23. 32-pin qfn (5 5 0.55 mm) lq32 3.5 3.5 e-pad (sawn) package outline, 001-42168 001-42168 *e
cy8c24x93 document number: 001-86894 rev. *b page 47 of 65 figure 24. 16-pin chip on lead (3 3 0.6 mm) lg16a/ld16a (sawn) package outline, 001-09116 figure 25. 48-pin qfn (6 6 0.6 mm) lq48a 4.6 4.6 e-pad (sawn) p ackage outline, 001-57280 001-09116 *h 001-57280 *e
cy8c24x93 document number: 001-86894 rev. *b page 48 of 65 figure 26. 48-pin qfn (7 7 1.0 mm) lt48a 5.1 5.1 e-pad (sawn) package outline, 001-13191 important notes for information on the preferred dimensions for mountin g qfn packages, see the following application note at http://www.amkor.com/products/n otes_papers/mlfappnote.pdf . pinned vias for thermal conduction are not required for the low power psoc device. 001-13191 *g
cy8c24x93 document number: 001-86894 rev. *b page 49 of 65 thermal impedances capacitance on crystal pins solder reflow specifications ta b l e 6 1 shows the solder reflow temperature limits that must not be exceeded. table 59. thermal impedances per package package typical ? ja [54] typical ? jc 16-pin qfn (no center pad) 33 ? c/w ? 32-pin qfn [55] 20 ? c/w ? 48-pin qfn (6 6 0.6 mm) [55] 25.20 ? c/w 3.04 ? c/w 48-pin qfn (7 7 1.0 mm) [55] 18 ? c/w ? table 60. typical package capacitance on crystal pins package package capacitance 32-pin qfn 3.2 pf 48-pin qfn 3.3 pf table 61. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 16-pin qfn 260 ? c 30 seconds 32-pin qfn 260 ? c 30 seconds 48-pin qfn (6 6 0.6 mm) 260 ? c 30 seconds 48-pin qfn (7 7 1.0 mm) 260 ? c 30 seconds notes 54. t j = t a + power ? ja . 55. to achieve the thermal impedance specified for the qfn package, the center thermal pad must be soldered to the pcb ground pl ane.
cy8c24x93 document number: 001-86894 rev. *b page 50 of 65 development tool selection software psoc designer? at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for over half a decade. psoc designer is available free of charge at http://www.cypress.com . psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice- cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits are sold at the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. psoc designer supports the adva nce emulation features also. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66a family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466a-24pxi 28-pdip chip samples evaluation tools all evaluation tools are sold at the cypress online store. for more information on pso c 1 kits, visit the link http://www.cypress. com/?rid=63754 device programmers all device programmers are purchased from the cypress online store.
cy8c24x93 document number: 001-86894 rev. *b page 51 of 65 ordering information the following table lists the cy8c24x93 psoc devices' key package features and ordering codes. ordering code definitions table 62. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) digital i/o pins analog inputs [56] xres pin usb adc supported by ocd 16-pin qfn (3 3 0.6 mm) cy8c24093-24lkxi 8 k 1 k 13 13 yes no yes no 32-pin qfn (5 5 0.6 mm) cy8c24193-24lqxi 8 k 1 k 28 28 yes no yes yes 32-pin qfn (5 5 0.6 mm) cy8c24293-24lqxi 16 k 2 k 28 28 yes no yes no 48-pin qfn (6 6 0.6 mm) cy8c24393-24lqxi 16 k 2 k 34 34 yes no yes no 48-pin qfn (7 7 1.0 mm) cy8c24493-24ltxi 32 k 2 k 36 36 yes yes yes yes 48-pin qfn (6 6 0.6 mm) cy8c24693-24lqxi 32 k 2 k 34 34 yes no yes no 48-pin qfn (ocd) (7 7 1.0 mm) CY8C240093-24LTXI 32 k 2 k 36 36 yes yes yes ? x = blank or t blank = tube; t = tape and reel temperature range: i = industrial pb-free package type: lk = 16-pin qfn; lq = 32-pin qfn or 48-pin qfn speed grade: 24 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress c24 x93 -24 x xx x cy 8 i note 56. dual-function digital i/o pins also connect to the common analog mux.
cy8c24x93 document number: 001-86894 rev. *b page 52 of 65 acronyms table 63. acronyms used in this document acronym description ac alternating current adc analog-to-digital converter api application programming interface cmos complementary metal oxide semiconductor cpu central processing unit dac digital-to-analog converter dc direct current eop end of packet fsr full scale range gpio general purpose input/output gui graphical user interface i 2 c inter-integrated circuit ice in-circuit emulator idac digital analog converter current ilo internal low speed oscillator imo internal main oscillator i/o input/output issp in-system serial programming lcd liquid crystal display ldo low dropout (regulator) lsb least-significant bit lvd low voltage detect mcu micro-controller unit mips mega instructions per second miso master in slave out mosi master out slave in msb most-significant bit ocd on-chip debugger por power on reset ppor precision power on reset psrr power supply rejection ratio pwrsys power system psoc ? programmable system-on-chip slimo slow internal main oscillator sram static random access memory snr signal to noise ratio qfn quad flat no-lead scl serial i2c clock sda serial i2c data sdata serial issp data spi serial peripheral interface ss slave select ssop shrink small outline package tc test controller usb universal serial bus usb d+ usb data+ usb d? usb data? wlcsp wafer level chip scale package xtal crystal table 63. acronyms us ed in this document (continued) acronym description
cy8c24x93 document number: 001-86894 rev. *b page 53 of 65 document conventions units of measure reference documents technical reference manual for cy8c24x93 devices in-system serial programming (issp) protocol for cy8c24x93 ( an2026c ) host sourced serial programming for cy8c24x93 devices ( an59389 ) numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h?, ?b?, or 0x are decimal. table 64. units of measure symbol unit of measure c degree celsius db decibel ff femtofarad g gram hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz ksps kilo samples per second k ? kilohm mhz megahertz m ? megaohm ? a microampere ? f microfarad ? h microhenry ? s microsecond ? w microwatt ma milliampere ms millisecond mv millivolt na nanoampere nf nanofarad ns nanosecond nv nanovolt w ohm pa picoampere pf picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second s sigma: one standard deviation v volt w watt
cy8c24x93 document number: 001-86894 rev. *b page 54 of 65 glossary crosspoint connection connection between any gpio combination via analog multiplexer bus. differential non-linearity ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one lsb apart. differential non-linearity is a measure of the worst case deviation from the ideal 1 lsb step. hold time hold time is the time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct. i 2 c it is a serial multi-master bus used to connect low speed peripherals to mcu. integral nonlinearity it is a term describing the maximum deviation between the idea l output of a dac/adc and the actual output level. latch-up current current at which the latch-up test is conducted according to jesd78 standard (at 125 degree celsius) power supply rejection ratio (psrr) the psrr is defined as th e ratio of the change in supply voltage to the corresponding change in output voltage of the device. setup time period r equired to prepare a device, machine, proc ess, or system for it to be ready to function. spi serial peripheral interface is a synchronous serial data link standard.
cy8c24x93 document number: 001-86894 rev. *b page 55 of 65 appendix a: silicon errata for the cy8c24093/293/393/693 family this section describes the errata for the cy8c24093/293/393/693 fa mily. details include errata trigger conditions, scope of imp act, available workarounds, and silicon revision applicability. contact your local cypress sales re presentative if you have questions. cy8c24093/293/393/693 qualification status product status: production released. cy8c24093/293/393/693 errata summary the following errata items apply to the cy8c24093/293/393/693 datasheet 001-86894. 1. doubletimer0 isr problem definition when programmable timer 0 is used in ?one-shot? mode by setting bit 1 of register 0,b0h (pt0_c fg), and the timer interrupt is used to wake the device from sleep, the inte rrupt service routine (isr) may be executed twice. parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode. scope of impact the isr may be executed twice. workaround in the isr, firmware should clear the one-shot bit with a statement such as ? and reg[b0h], fdh ? fix status will not be fixed changes none
cy8c24x93 document number: 001-86894 rev. *b page 56 of 65 2. missed gpio interrupt problem definition when in sleep mode, if a gpio interrupt happens simultaneously wi th a timer0 or sleep timer interrupt, the gpio interrupt may be missed, and the corresponding gpio isr not run. parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling sleep mode, then having gpio interrupt o ccur simultaneously with a timer 0 or sleep timer interrupt. scope of impact the gpio interrupt service routine will not be run. workaround the system should be architected such that a missed gpio interrupt may be detected. for example, if a gpio is used to wake the system to perform some function, the system should detect if the function is not performed, and re-issue the gpio interrupt . alternatively, if a gpio interrupt is required to wake the system, then firmware should disable the sleep timer and timer0. alternatively, the isr?s for sleep timer and timer0 should manua lly check the state of the gpio to determine if the host system has attempted to gener ate a gpio interrupt. fix status will not be fixed changes none 3. missed interrupt during transition to sleep problem definition if an interrupt is posted a short time (within 2.5 cpu cycles) before firmware commands the devic e to sleep, the interrupt will be missed. parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling sleep mode just prior to an interrupt. scope of impact the relevant interrupt serv ice routine will not be run. workaround none. fix status will not be fixed changes none
cy8c24x93 document number: 001-86894 rev. *b page 57 of 65 4. wakeup from sleep with analog interrupt problem definition device wakes up from sleep when an analog interrupt is trigger parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 c or above scope of impact device unexpectedly wakes up from sleep workaround disable the analog interrupt before entering sleep and turn it back on upon wake-up. fix status will not be fixed changes none
cy8c24x93 document number: 001-86894 rev. *b page 58 of 65 5. wake-up from sleep with hardware i2c address match on pins p1[0], p1[1] problem definition i2c interface needs 20 ns hold time on sda line with respect to falling edge of scl, to wake-up from sleep using i2c hardware address match event. parameters affected t hd;dat increased to 20 ns from 0 ns trigger condition(s) this is an issue only when all these three conditions are met: 1) p1.0 and p1.1 are used as i2c pins, 2) wakeup from sleep with hardware address match feature is enabled, and 3) i2c master does not provide 20 ns hold time on sda with respect to falling edge of scl. scope of impact these trigger conditions cause the device to never wake-up from sleep based on i2c address match event workaround for a design that meets all of the trigger conditions, the follo wing suggested circuit has to be implemented as a work-around. the r and c values proposed are 100 ohm and 200 pf respectively. fix status will not be fixed changes none cy8c24093/ 293/393/693
cy8c24x93 document number: 001-86894 rev. *b page 59 of 65 6. i2c port pin pull- up supply voltage problem definition pull-up resistor on i2c interface cannot be connected to a supply voltage that is greater than 0.7 v of cy8c24093/293/393/693 v dd . parameters affected none. trigger condition(s) this problem occurs only when the i2c master is powered at a higher voltage than cy8c24093/293/393/693. scope of impact this trigger condition will corrupt the i2c communication betw een the i2c host and the cy8c 24093/293/393/693 controller. workaround i2c master cannot be powered at a supply vo ltage that is greater than 0.7 v compared to cy8c24093/293/393/693 supply voltage. fix status will not be fixed changes none 7. port1 pin voltage problem definition pull-up resistor on port1 pins cannot be connected to a voltage that is greater than 0.7 v highe r than cy8c24093/293/393/693 v dd . parameters affected none. trigger condition(s) this problem occurs only when port1 pi ns are at voltage 0.7 v higher than v dd of cy8c24093/293/393/693. scope of impact this trigger condition will not allow cy8c 24093/293/393/693 to drive the ou tput signal on port1 pins, input path is unaffected by this condition. workaround port1 should not be connected to a higher voltage than v dd of cy8c24093/293/393/693. fix status will not be fixed changes none
cy8c24x93 document number: 001-86894 rev. *b page 60 of 65 appendix b: silicon errata for the psoc ? cy8c24193/493 families this section describes the errata for the psoc ? cy8c24193/493 families. details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. contact your local cypress sales re presentative if you have questions. cy8c24193/493 qualification status product status: production released. cy8c24193/493 errata summary the following errata items apply to the cy8c24193/493 datasheet 001-86894. 1. wakeup from sleep may intermittently fail problem definition when the device is put to sleep in standby or i2c_usb mode an d the bandgap circuit is refreshed less frequently than every 8 ms (default), the device may not come out of sleep when a sleep-ending input is received. parameters affected none trigger condition(s) by default, when the device is in the standby or i2c_usb slee p modes, the bandgap circuit is powered-up approximately every 8 ms to facilitate detection of por or lvd events. this interv al can be lengthened or the periodic power-up disabled to reduce sl eep current by setting the alt_buzz bits in the slp_cfg2 register or the disable buzz bit in the osc_cr0 register respectively. if the bandgap circuit refresh interval is set longer than the default 8 ms, the device may fail to wakeup from sleep and enter a locked up state that can only be recovere d by watchdog reset, xres, or por. scope of impact the trigger conditions outlined above may cause the device to never wakeup. workaround prior to entering standby or i2c_usb sleep modes, do not lengthen or disable the bandg ap refresh interval by manipulating the alt_buzz bits in the slp_cfg2 register or the disable buzz bit in the osc_cr0 register respectively. fix status this issue will not be corrected in the next silicon revision.
cy8c24x93 document number: 001-86894 rev. *b page 61 of 65 2. i 2 c errors problem definition the i 2 c block exhibits occasional data and bus corruption errors when the i 2 c master initiates transactions while the device is transitioning in to or out of sleep mode. parameters affected affects reliability of i 2 c communication to device, and between i 2 c master and third party i 2 c slaves. trigger condition(s) triggered by transitions into and out of the device?s sleep mode. scope of impact data errors result in incorrect data reported to the i 2 c master, or incorrect data received from the master by the device. bus corruption errors can corrupt data in transactions between the i 2 c master and third party i 2 c slaves. workaround firmware workarounds are available in firmware. genera lly the workaround consists of disconnecting the i 2 c block from the bus prior to going to sleep modes. i 2 c transactions during sleep are supported by a protoc ol in which the master wakes the device prior to the i 2 c transaction. fix status to be fixed in future silicon. changes none 3. doubletimer0 isr problem definition when programmable timer 0 is used in ?one-shot? mode by setting bit 1 of register 0,b0h (pt0_c fg), and the timer interrupt is used to wake the device from sleep, the inte rrupt service routine (isr) may be executed twice. parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode. scope of impact the isr may be executed twice. workaround in the isr, firmware should clear the one-shot bit with a statement such as ? and reg[b0h], fdh ? fix status will not be fixed changes none
cy8c24x93 document number: 001-86894 rev. *b page 62 of 65 4. missed gpio interrupt problem definition when in sleep mode, if a gpio interrupt happens simultaneously wi th a timer0 or sleep timer interrupt, the gpio interrupt may be missed, and the corresponding gpio isr not run. parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling sleep mode, then having gpio interrupt o ccur simultaneously with a timer 0 or sleep timer interrupt. scope of impact the gpio interrupt service routine will not be run. workaround the system should be architected such that a missed gpio interrupt may be detected. for example, if a gpio is used to wake the system to perform some function, the system should detect if the function is not performed, and re-issue the gpio interrupt . alternatively, if a gpio interrupt is required to wake the system, then firmware should disable the sleep timer and timer0. alternatively, the isr?s for sleep timer and timer0 should manua lly check the state of the gpio to determine if the host system has attempted to gener ate a gpio interrupt. fix status will not be fixed changes none 5. missed interrupt during transition to sleep problem definition if an interrupt is posted a short time (within 2.5 cpu cycles) before firmware commands the devic e to sleep, the interrupt will be missed. parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling sleep mode just prior to an interrupt. scope of impact the relevant interrupt serv ice routine will not be run. workaround none. fix status will not be fixed changes none
cy8c24x93 document number: 001-86894 rev. *b page 63 of 65 6. wakeup from sleep with analog interrupt problem definition device wakes up from sleep when an analog interrupt is trigger parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 c or above scope of impact device unexpectedly wakes up from sleep workaround disable the analog interrupt before entering sleep and turn it back on upon wakeup. fix status will not be fixed changes none
cy8c24x93 document number: 001-86894 rev. *b page 64 of 65 document history page document title: cy8c24x93, psoc ? programmable system-on-chip document number: 001-86894 revision ecn orig. of change submission date description of change ** 3947416 amka 04/02/2013 new data sheet. *a 3971208 amka 04/30/2013 changed status from preliminary to final. updated features . updated psoc ? functional overview (updated analog system (updated idac ), updated additional system resources ). updated ordering information (updated part numbers). *b 4009884 amka 05/24/2013 updated logic block diagram . updated getting started (updated silicon errata ). updated development tool selection (updated evaluation tools (removed cy3210-psoceval1)). updated reference documents . added appendix a: silicon errata for the cy8c24093/293/393/693 family . added appendix b: silicon errata for the psoc? cy8c24193/493 families .
document number: 001-86894 rev. *b revised may 24, 2013 page 65 of 65 psoc designer? and psoc programmer? are trademarks and psoc ? and capsense ? are registered trademarks of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c24x93 ? cypress semiconductor corporation, 2013. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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